Project Overview

The ability to create a custom digital ASIC (Application Specific Integrated Circuit) is often locked behind high barriers to entry and restricted to industry professionals. Many different groups would benefit from a method to create custom ASIC designs including research groups, future senior design teams, and other students who would benefit from the experience of designing custom parts. We will submit a design to the eFabless platform to test the limits of what they can manufacture and determine the limits of their processes including clock gating, power management, custom logic cells, and various other components of the framework. This learning will be passed down to future users who will use our design as a reference in creating their own for research or other learning tasks.

In specific, our group will perform the following tasks to test the limits of the eFabless MPW system:

• Implement clock gating to show the ability for designers to limit the power usage of unused components
• Instantiate several standard cells provided by eFabless to show how to manually select and use specific cells from the library
• Explore creating custom logic cells to possibly allow for higher density designs and expand beyond the standard cells provided
• Ensure the design is modular so each submodule can be tested independently and one error cannot cause the entire project to fail
• Use the wishbone bus provided in the wrapper project to learn how the wishbone bus operates in hardware
• Use the provided tools to perform Register Transfer Language (RTL) simulations and Gate Level (GL) simulations to verify a design prior to fabrication
• Provide any additional documentation on how we implemented each new portion of our project for future designers to reference

Final hardened GDS